1. Field of the Invention
The present invention relates to a semiconductor packaging technology and, more particularly, to a semiconductor chip stack structure and method for forming the same.
2. Description of the Related Art
To provide improved performance, manufacturers of integrated circuit (IC) chips continually strive to increase packaging density, which has led to the development of, for example, a three-dimensional chip stack technology. In this technology, typically, after the wafer is separated into individual chips, the chips are stacked before or after they are packaged.
The three-dimensional stack of the packaged chips, however, increases the stack height due to individual package thickness. In contrast, the three-dimensional stack of the non-packaged (“bare”) chips is relatively thinner, lighter and smaller.
Among the various chip stack structures of the non-packaged chips, a stack structure having a pyramid configuration (a relatively smaller upper chip stacked on a lower chip) is known to reduce the stack height. On the other hand, if the upper chip is equal to or larger than the lower chip, a spacer is required between the upper and lower chips for preventing electrical interference that may occur when a bonding wire on the lower chip touches a bottom surface of the upper chip. Such a spacer, unfortunately, causes a substantial increase in the stack height.
FIG. 1 shows a conventional chip stack structure 10. In the chip stack, a semiconductor chip 19 (“a second chip”) is stacked on a lower semiconductor chip 14 (“a first chip”), using a liquid adhesive 17 containing insulating balls 18 as the spacer. The liquid adhesive 17 is applied on the first chip 14 mounted on a substrate 11. The first chip 14 is electrically connected with a wiring pattern 13 of the substrate 11 by a bonding wire 16. When the second chip 19 is stacked on the first chip 14, the bonding wire 16 may touch the second chip 19. Thus, electrical interference between them may occur. The liquid adhesive 17 is therefore required so that the second chip 19 may not directly contact with the bonding wire 16. The liquid adhesive 17 may contain the insulating balls 18, each having a larger diameter than the highest point of the bonding wire 16 from the top surface of the first chip 14. Reference character S1 in FIG. 1 specifies a space between the first chip 14 and the second chip 19.
The wire bonding between the first chip 14 and the substrate 11 may be carried out by a conventional wire bonding process, such as a ball bonding process on the first chip 14 and subsequently a stitch bonding process on the wiring pattern of the substrate 11.
FIG. 2 shows another conventional chip stack structure 20 in which an insulating adhesive tape 27 serves as a spacer between the first chip 24 and the second chip 29. The insulating adhesive tape 27 should be thicker than the highest point of the bonding wire 26 from the top surface of the first chip 24. Reference character S2 in FIG. 2 specifies a space between the first chip 24 and the second chip 29.
As described above, the conventional chip stack technology has a disadvantage of increasing the total stack height due to the spacer required between the semiconductor chips.